Feedback compensation detector for a direct conversion transmitter

ABSTRACT

A feedback compensation detector for a direct conversion transmitter includes a baseband processor, a direct up-converter, an antenna, and an impairment detection and compensation feedback circuit. The baseband processor generates an in-phase (I) baseband signal and a quadrature-phase (Q) baseband signal. The direct up-converter is coupled to the baseband processor, and combines the I and Q baseband signals with an RF carrier signal to generate an RF output signal. The antenna is coupled to the direct up-converter, and transmits the RF output signal. The impairment detection and compensation feedback circuit is coupled to the RF output signal and the I and Q baseband signals. The impairment detection and compensation feedback circuit down-converts the RF output signal to generate an intermediate frequency (IF) signal, measures as least one signal impairment in the IF signal, and pre-distorts the I and Q baseband signals to compensate for the measured signal impairment.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a continuation of U.S. application Ser. No.10/145,930, filed on May 15, 2002, which claims priority from and isrelated to the following prior application: Feedback CompensationDetector For A Direct Conversion Transmitter And Method Of OperatingSame, U.S. Provisional Application No. 60/291,239, filed May 15, 2001.These prior applications, including the entirety of the writtendescriptions and drawing figures, are hereby incorporated into thepresent application by reference.

FIELD OF THE INVENTION

This application relates generally to the field of radio frequency (RF)signal transmission. More specifically, a feedback compensation detectorfor a direct conversion transmitter is provided that is particularlywell-suited for use in a Quadrature Amplitude Modulated (QAM)transmitter, but may also provide utility in any transmitter that usessufficiently independent modulation on the two quadrature axes (I andQ), such as a Code Division Multiple Access (CDMA) transmitter, aWideband Direct Sequence CDMA (WCDMA) transmitter, or a Global Systemfor Mobile Communications (GSM) transmitter.

BACKGROUND OF THE INVENTION

Direct conversion transmitters are known. In a typical direct conversiontransmitter chain, baseband in-phase (I) and quadrature-phase (Q)digital signals are converted to analog signals, filtered, amplified andmodulated to form an analog baseband signal. The analog baseband signalis then converted to a radio frequency (RF) signal at a carrierfrequency, amplified, filtered, and transmitted via an antenna. Suchtransmitter chains, however, typically propagate signal impairmentswhich are often resultant from channel delays, imbalances, and othersignal distortions occurring within the transmitter chain.

SUMMARY

A feedback compensation detector for a direct conversion transmitterincludes a baseband processor, a direct up-converter, an antenna, and animpairment detection and compensation feedback circuit. The basebandprocessor generates an in-phase (I) baseband signal and aquadrature-phase (Q) baseband signal. The direct up-converter is coupledto the baseband processor, and combines the I and Q baseband signalswith an RF carrier signal to generate an RF output signal. The antennais coupled to the direct up-converter, and transmits the RF outputsignal. The impairment detection and compensation feedback circuit iscoupled to the RF output signal and the I and Q baseband signals. Theimpairment detection and compensation feedback circuit down-converts theRF output signal to generate an intermediate frequency (IF) signal,measures as least one signal impairment in the IF signal, andpre-distorts the I and Q baseband signals to compensate for the measuredsignal impairment.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a direct up-conversion transmitter chainwith an impairment compensation feedback path;

FIG. 2 is a more detailed block diagram of the direct up-converter shownin FIG. 1;

FIG. 3 is a block diagram of the direct up-conversion transmitter chainshown in FIG. 1 with a more detailed illustration of the impairmentdetector;

FIG. 4 is a more detailed block diagram of the impairment compensatorshown in FIG. 1;

FIG. 5 is a block diagram of a timing estimator circuit for estimatingthe in-phase (I) component delay, T_(ie), shown in FIG. 4;

FIG. 6 is a block diagram of a direct up-conversion transmitter chainhaving an automatic gain control (AGC) correction loop in the impairmentcompensation feedback path;

FIG. 7 is a block diagram of a direct up-conversion transmitter chainhaving a local oscillator (LO) leakage nulling loop in the impairmentcompensation feedback path;

FIG. 8 is a block diagram of a direct up-conversion transmitter chainhaving a quadrature imbalance compensation loop in the impairmentcompensation feedback path;

FIG. 9 is a block diagram of a direct up-conversion transmitter chainhaving a differential timing error compensation loop in the impairmentcompensation feedback path;

FIG. 10 is a block diagram of an exemplary temperature and supplyvoltage compensation circuit for the impairment detector shown in FIGS.1, 3, and 6-9;

FIG. 11 is a flow diagram of a method for iteratively estimating thevalues of the ambient temperature T and battery supply voltage V_(d)shown in FIG. 10; and

FIG. 12 is a flow diagram illustrating an exemplary method for operatingthe feedback compensation detector described above with reference toFIGS. 1-9.

DETAILED DESCRIPTION

Impairment Compensation Feedback Path

Referring now to the drawing figures, FIG. 1 is a block diagram of adirect up-conversion transmitter chain 100 with an impairmentcompensation feedback path. The transmitter chain 100 includes abaseband processor 110, an impairment compensator 112, a directup-converter 114, and an impairment detector 116. The baseband processor110 may, for example, be a digital signal processor (DSP), a centralprocessing unit (CPU), or some other type of processing device or logiccircuitry. The transmitter chain also includes a pair ofdigital-to-analog converters DACs 118, a frequency synthesizer 120, aband pass filter 122, and an antenna 124. Operationally, the impairmentdetector 116 measures signal impairments in the direct up-converteroutput 121, and generates a feedback signal 126 that is coupled to theimpairment compensator 112. Exemplary signal impairments which may bedetected by the impairment detector 116 are described below withreference to FIG. 3.

The baseband processor 110 generates in-phase (I) and quadrature-phase(Q) digital baseband signals for RF transmission. The I and Q basebandsignals are modified prior to analog conversion by the impairmentcompensator 112, as described below. The modified baseband signals arethen converted into the analog domain by the DACs 118 and are coupled tothe direct up-converter 114 which combines the analog baseband signalswith an RF carrier signal 119 from the frequency synthesizer 120. Anexemplary direct up-converter 114 is described below with reference toFIG. 2. The RF output signal 121 from the direct up-converter 114 isfiltered by the band pass filter 122, and is transmitted by the antenna124. In addition, the RF output signal 121 is coupled to the impairmentdetector 116 which measures signal impairments, as described below, andgenerates the feedback signal 126 that is coupled to the impairmentcompensator 112. The feedback signal 126 is used by the impairmentcompensator 112 to pre-distort the I and Q baseband signals such thatthe pre-distortion cancels any actual distortion caused by impairmentsin the direct up-converter 114.

FIG. 2 is a more detailed block diagram 200 of the direct up-converter114 shown in FIG. 1. The direct up-converter 114 includes a pair of lowpass filters 202, a pair of amplifiers 204, a quadrature up-converter206, an automatic gain control (AGC) amplifier 208, a band pass filter210, and a power amplifier (PA) 212.

The analog I and Q baseband signals from the DACs 118 are received asinputs to the direct up-converter 114. The I and Q inputs are thenfiltered by the pair of low pass filters 202, amplified by the pair ofamplifiers 204, and coupled as inputs to the quadrature up-converter206. The quadrature up-converter 206 also receives a carrier signal (F1)from the frequency synthesizer 120, and combines the analog basebandsignals with the carrier signal (F1) to generate a radio frequency (RF)signal having a carrier frequency of F1. The RF signal is amplified bythe AGC amplifier 208 in order to provide the necessary gain to drivethe power amplifier (PA) 212. The PA 212 further amplifies the RF signalto generate the RF output signal 121.

FIG. 3 is a block diagram 300 of the direct up-conversion transmitterchain 100 shown in FIG. 1 with a more detailed illustration of theimpairment detector 116. The impairment detector 116 includes a variableattenuator 302, a down-conversion mixer 304, a band pass filter 306, ananalog-to-digital (A/D) converter 308, and a impairment detectorprocessor 310. The impairment detector processor 310 may, for example,be a digital signal processor (DSP), a central processing unit (CPU), orsome other type of processing device or logic circuitry. In oneembodiment, the processing functions of the impairment detectorprocessor 310 and the baseband processor 110 described above may beperformed by the same processing device.

The RF output signal 121 from the direct up-converter 114 is sampled bythe variable attenuator 302 which reduces the gain of the signal 121 toan appropriate power range for the down-conversion mixer 304. The outputfrom the variable attenuator 302 is coupled to the down-conversion mixer304 along with a local oscillator (LO) signal 303 generated by thefrequency synthesizer 120, which has a different frequency (F₂) than thefrequency (F₁) of the RF carrier signal 119. The intermediate frequency(IF) output of the down-conversion mixer 304 thus has a center frequencythat is substantially equal to the difference between the frequencies ofthe LO signal 303 and the RF carrier signal 119 (F₁-F₂).

The band pass filter 306 is centered at the intermediate frequency(F₁-F₂), and filters the IF output to a pre-determined passband togenerate an analog impairment signal z(t), where z is a time domainfunction and t is time. The analog impairment signal z(t) is sampled bythe A/D converter 308, and the resulting digital signal is coupled tothe impairment detector processor 310 and may also be stored in a memorydevice, such as a buffer memory, via the processor 310.

The impairment detector processor 310 is configured to estimate one ormore impairments present in the RF signal 121. For instance, theimpairment detector processor 310 may be configured to estimate theoverall gain of the up-converter chain 100, a leakage component from theLO signal 303, a phase or amplitude imbalance in the quadratureup-converter 206, a differential delay between the I and Q basebandchannels, or some other signal impairment. The feedback signal 126 fromthe impairment detector 116 is generated by the impairment detectorprocessor 310 based on the impairments detected in the RF signal 121 andis applied to the I and Q baseband signals in the impairment compensator112. In addition, the impairment detector processor 310 generates anattenuation control signal 312 that is fed back to control the negativegain applied by the variable attenuator 302. The relationship betweenthe operations of the impairment detector 116 and the impairmentcompensator 112, including the estimation of signal impairments by theimpairment detector processor 310, is described below with reference toFIGS. 5-9.

FIG. 4 is a more detailed block diagram 400 of the impairmentcompensator 112 shown in FIG. 1. The impairment compensator 112 includesin-phase and quadrature-phase delay compensation blocks 402, 404,in-phase and quadrature-phase bias compensation adders 406, 408, alinear compensation block 410, and in-phase and quadrature-phase gainmultipliers 412, 414. Also illustrated are the in-phase (I) andquadrature-phase (Q) digital baseband signals from the basebandprocessor 110, denoted in the time domain as g_(i)(t) and g_(q)(t)respectively.

The in-phase and quadrature-phase baseband signals g_(i)(t) and g_(q)(t)are advanced by estimated I and Q component delay values, T_(ie) andT_(qe), in the delay compensation blocks 402, 404. The estimated I and Qcomponent delay values T_(ie) and T_(qe) compensate for I and Qcomponent delays from the transmitter chain 100, and are received asinputs from the impairment detector 116. An exemplary method forestimating the I and Q component delay values, T_(ie) and T_(qe), isdescribed below with reference to FIG. 5.

The in-phase and quadrature-phase outputs from the delay compensationblocks 402, 404 are coupled as positive inputs to the in-phase andquadrature-phase bias compensation adders 406, 408. In addition,estimated in-phase and quadrature-phase bias offset values, b_(ie) andb_(qe), derived by the impairment detector 116, are coupled as negativeinputs to the in-phase and quadrature-phase bias compensation adders406, 408. The bais offset values, b_(ie) and b_(qe), compensate fordirect-current (DC) bias caused, for example, by leakage of the LOsignal 303 in the RF output signal 121 (see FIG. 3). An exemplary methodfor estimating the bias offset values, b_(ie) and b_(qe), is describedbelow.

The in-phase and quadrature-phase outputs from the bias compensationadders 406, 408 are coupled as inputs to the linear compensation block410 along with estimated phase and amplitude imbalance parameters, e_(e)and f_(e), calculated by the impairment detector 116. Using theestimated phase and amplitude imbalance parameters, e_(e) and f_(e), thelinear compensation block 410 applies an inverse model of the phase andamplitude imbalance in the quadrature up-converter 206, and outputsbalanced in-phase and quadrature-phase signal components. An exemplarymethod for estimating the phase and amplitude imbalance parameters,e_(e) and f_(e), is described below.

The balanced outputs from the linear compensation block 410 are coupledas inputs to the in-phase and quadrature-phase gain multipliers 412,414. Also coupled as inputs to the gain multipliers 412, 414 is ascaling factor, G_(des)/G_(oe), which adjusts the in-phase andquadrature-phase signals to compensate for gain imbalances. Thenumerator of the scaling factor, G_(des), represents the desired gainfor the transmitter chain 100, and the denominator, G_(oe), is theestimated actual gain. The desired gain G_(des) is pre-selectedaccording to the desired characteristics of the transmitter chain 100.The estimated actual gain G_(oe) may be calculated by the impairmentdetector 116, as described below. The in-phase and quadrature-phaseoutputs from the gain multipliers 412, 414 are coupled to the DACs 118,as described above with reference to FIG. 1.

In one alternative embodiment, the impairment detector 112 may beimplemented as a software application executing on the basebandprocessor 110 or on some other processing device.

Estimating I and Q Component Delays (T_(ie) and T_(ge))

FIG. 5 is a block diagram 500 of a timing estimator circuit forestimating the I component delay, T_(ie), shown in FIG. 4. The timingestimator circuit 500 may, for example, be implemented by the impairmentdetector processor 310, and includes a first mixer 502, a second mixer504, and an integrator 506.

The analog impairment signal z(t), described above with reference toFIG. 3, is coupled as an input to the first mixer 502 along with adelayed in-phase baseband signal g_(i)(t-T_(ie)) 508. The delayedin-phase baseband signal g_(i)(t-T_(ie)) 508 is delayed by an estimatedvalue for the I component delay T_(ie). The output from the first mixer504 is then coupled as an input to the second mixer 504 along with asampling phase adjustment parameter 510. The sampling phase adjustmentparameter 510 may be calculated as: cos(2π(F₁-F₂)t+p); where (F₁-F₂) isthe frequency of the IF output from the down-conversion mixer 304 shownin FIG. 3, and p is a phase parameter. The output from the second mixer504 is fed into the integrator 506, which integrates the signal over asampling epoch (M/(F₁-F₂)) to produce an output signal (Y) 512, where Mis an integer parameter corresponding to the number of integrationcycles.

Operationally, the estimated I component delay, T_(ie), is calculated byvarying the values of T_(ie) and p until a maximum value is obtained forthe timing estimator output (Y) 512. The maximum value for Y may beapproximated, for example, by calculating Y 512 over a pre-determinedrange of the variables T_(ie) and p. The value of T_(ie) that results inthe maximum timing estimator output (Y) 512 is an estimate of the totalin-phase component delay.

The estimated Q component delay, T_(iq), may be calculated using atiming estimator circuit similar to the circuit 500 shown in FIG. 5 inwhich the delayed in-phase baseband signal (g_(i)(t-T_(ie))) is replacedwith a delayed quadrature-phase baseband signal (g_(q)(t-T_(iq))).

Estimating Phase, Amplitude, and Gain Imbalance (e_(e), and G_(oe))

Referring again to FIG. 4, the linear compensation block 410 uses thephase and amplitude parameters e_(e) and f_(e) to compensate for phaseand amplitude imbalance in the quadrature up-converter 206, and thein-phase and quadrature-phase gain multipliers 412, 414 use the scalingfactor G_(des)/G_(oe) to balance the gain. The phase and amplitudeparameters e_(e) and f_(e) and the overall gain G_(oe) may be estimatedfrom the analog impairment signal z(t) described above with reference toFIG. 3. The subscript “e” or “est” as used within this applicationdenotes that the value for the given parameter is an estimated value.

The analog impairment signal z(t) may be expressed by the followingequation:z(t) = (C(t)a + S(t)c) * g_(ieq)(t − T_(i)) + (C(t)b + S(t)d) * g_(qeq)(t − T_(q));${{where}:{\begin{matrix}{{{g_{ieq}(t)} = {{g_{i}\left( {t - T_{i}} \right)} + b_{i}}};} \\{{{g_{qeq}(t)} = {{g_{q}\left( {t - T_{q}} \right)} + b_{q}}};} \\{{{C(t)} = {\cos\left( {2\quad{\pi\left( {F_{1} - F_{2}} \right)}t} \right)}};} \\{{{S(t)} = {\sin\left( {2\quad{\pi\left( {{F1} - {F2}} \right)}t} \right)}};{and}}\end{matrix}\begin{bmatrix}a & b \\c & d\end{bmatrix}}} = {{{G_{o}\begin{bmatrix}{\cos\left( \phi_{o} \right)} & {\sin\left( \phi_{o} \right)} \\{- {\sin\left( \phi_{o} \right)}} & {\cos\left( \phi_{o} \right)}\end{bmatrix}}\begin{bmatrix}1 & 0 \\e & f\end{bmatrix}}.}$

The matrix coefficients {a, b, c, d} represent the model of the impairedquadrature up-converter with a random start phase φ_(o), and may beestimated by sampling z(t). In addition, since the I and Q time delays,T_(i) and T_(q), are independent of other impairments, they may beassumed to be equal to zero (0) for the purposes of estimating thephase, amplitude, and gain imbalance parameters, e_(e), f_(e), andG_(oe).

Assume that z(t) is sampled such that z(n) is the sample of z(t) att=nT_(s), where the value of n ranges from 0 to (N-1) andN=M(T_(s)(F₁-F₂))⁻¹, and where M is an integer parameter correspondingto the number of integration cycles. Also assume that g_(i)(t) andg_(q)(t) are independent random processes with zero mean. Then, thematrix coefficients {a, b, c, d} may be estimated as follows:$\begin{matrix}{{a_{e} = \frac{\sum\limits_{n = 0}^{N - 1}\quad{{z(n)}{C(n)}{g_{i}(n)}}}{\sum\limits_{n = 0}^{N - 1}\quad{\left( {C(n)} \right)^{2}\left( {g_{i}(n)} \right)^{2}}}};} & {{b_{e} = \frac{\sum\limits_{n = 0}^{N - 1}\quad{{z(n)}{C(n)}{g_{q}(n)}}}{\sum\limits_{n = 0}^{N - 1}\quad{\left( {C(n)} \right)^{2}\left( {g_{q}(n)} \right)^{2}}}};} \\{{c_{e} = \frac{\sum\limits_{n = 0}^{N - 1}\quad{{z(n)}{S(n)}{g_{i}(n)}}}{\sum\limits_{n = 0}^{N - 1}\quad{\left( {S(n)} \right)^{2}\left( {g_{i}(n)} \right)^{2}}}};{and}} & {d_{e} = {\frac{\sum\limits_{n = 0}^{N - 1}\quad{{z(n)}{S(n)}{g_{q}(n)}}}{\sum\limits_{n = 0}^{N - 1}\quad{\left( {S(n)} \right)^{2}\left( {g_{q}(n)} \right)^{2}}}.}}\end{matrix}$

The estimated matrix coefficients {a_(e), b_(e), c_(e), d_(e)} may thenbe used to estimate the phase, amplitude, and gain imbalance parameters,e_(e), f_(e), and G_(oe), as follows: $\begin{matrix}{{e_{e} = \frac{{d_{e}c_{e}} + {b_{e}a_{e}}}{{a_{e}d_{e}} - {c_{e}b_{e}}}};} \\{{f_{e} = \frac{d_{e}^{2} + b_{e}^{2}}{{a_{e}d_{e}} - {c_{e}b_{e}}}};{and}} \\{G_{oe} = {\frac{{a_{e}d_{e}} - {c_{e}b_{e}}}{\sqrt{b_{e}^{2} + d_{e}^{2}}}.}}\end{matrix}$Estimating Bias Offset (b_(ie) and b_(qe))

With reference to FIG. 4, the in-phase and quadrature-phase delaycompensation blocks 402, 404 offset the I and Q baseband signals byin-phase and quadrature-phase bias parameters b_(ie) and b_(qe). Thebias parameters, b_(ie) and b_(qe), may be estimated from the analogimpairment signal z(t) independently of the other impairment parameterse_(e), f_(e), and G_(oe). The analog impairment signal z(t) 126 may thusbe expressed as:${z(t)} = \left\lbrack {{{{\cos\left( {{\phi(t)}{\sin\left( {\phi(t)} \right)}} \right\rbrack}{{G_{0}\begin{bmatrix}1 & 0 \\e & f\end{bmatrix}}\begin{bmatrix}b_{i} \\b_{q}\end{bmatrix}}} = {{\begin{bmatrix}C & S\end{bmatrix}\begin{bmatrix}a & b \\c & d\end{bmatrix}}\begin{bmatrix}b_{i} \\b_{q}\end{bmatrix}}};} \right.$such that:z(t)=(Ca+Sc)b _(i)+(Cb+Sd)b _(q).

The term (Ca+Sc) may be regarded as a vector in the two-dimensionalHilbert space of C(t) and S(t), and an orthogonal vector to (Ca+Sc) is(Cc-Sa). Consequently<(Ca+Sc)(Cc-Sa)>=0, which allows the parametersb_(i) and b_(q) to be extracted from the equation. Thus estimates ofb_(i) and b_(q), denoted as b_(ie) and b_(qe), may be derived as:$\begin{matrix}{{b_{ie} = {\frac{\sum\limits_{n = 0}^{N - 1}\quad{{z(n)}\left( {{{C(n)}c_{e}} - {{S(n)}a_{e}}} \right)}}{\sum\limits_{n = 0}^{N - 1}\quad{\left( {{{C(n)}c_{e}} - {{S(n)}a_{e}}} \right)\left( {{{C(n)}b_{e}} + {{S(n)}d_{e}}} \right)}} = \frac{2{\sum\limits_{n = 0}^{N - 1}\quad{{z(n)}\left( {{{C(n)}c_{e}} - {{S(n)}a_{e}}} \right)}}}{{a_{e}d_{e}} - {b_{e}c_{e}}}}};{and}} \\{b_{qe} = {\frac{\sum\limits_{n = 0}^{N - 1}\quad{{z(n)}\left( {{{C(n)}d_{e}} - {{S(n)}b_{e}}} \right)}}{{a_{e}d_{e}} - {b_{e}c_{e}}}.}}\end{matrix}$Automatic Gain Control Correction Loop

FIG. 6 is a block diagram of a direct up-conversion transmitter chain600 having an automatic gain control (AGC) correction loop in theimpairment compensation feedback path. This transmitter chain 600 issimilar to the transmitter chain 100 described above with reference toFIGS. 1-5, except the feedback path includes a comparator 602, a mixer604, and a gain correction loop 606. In operation, the AGC loopcompensates for errors in the AGC amplifier 208 described above withreference to FIG. 2.

The comparator 602 has a positive input coupled to the estimated gainG_(oe) from the impairment detector 116 and a negative input coupled tothe pre-selected desired gain G_(des). The comparator 602 subtracts thedesired gain G_(des) from the estimated gain G_(oe) to generate acomparator output that is coupled as an input to the mixer 604. Themixer 604 applies a pre-selected gain coefficient K_(G) to thecomparator output, and generates a mixer output that is coupled as aninput to the gain correction loop 606. The gain correction loop 606 may,for example, be a first order correction loop that generates again-compensated output G_(comp) that may be expressed by the equation:G_(comp)=G_(comp)−KG(G_(oe)−G_(des)). Accordingly, the speed at whichthe AGC correction loop 606 will track AGC errors may be increased byincreasing the value of the gain coefficient K_(G).

The gain-compensated output, G_(comp), from the AGC correction loop 606is coupled as the inputs to the gain multipliers 412, 414 in theimpairment compensator 112, as described above with reference to FIG. 4.It should be understood, that although the impairment compensator 112illustrated in FIG. 6 has been simplified to show only the gainmultipliers 412, 414, the impairment compensator 112 may include theadditional elements described above with reference to FIG. 4.

Local Oscillator Leakage Nulling Loop

FIG. 7 is a block diagram of a direct up-conversion transmitter chain700 having a local oscillator (LO) leakage nulling loop 702 in theimpairment compensation feedback path. This transmitter chain 700 issimilar to the transmitter chain 100 described above with reference toFIGS. 1-5, except for the inclusion of the LO leakage nulling loop 702in the feedback path. In operation, the LO leakage nulling loop 702corrects for corruption of the RF signal 121 caused by the LO signal303.

The LO signal 303 may be suppressed in the RF signal 121 by nulling theDC bias parameters b_(ie) and b_(qe). The LO leakage nulling loop 702accomplishes this by implementing a first order correction loop thatapplies a pre-selected bias coefficient K_(b), and generates compensatedin-phase and quadrature-phase bias offset parameters, b_(icomp) andb_(qcomp), according to the equations:b _(icomp) =b _(icomp) −K _(b) b _(ie); andb _(qcomp) =b _(qcomp) −K _(b) b _(qe).

The compensated in-phase and quadrature-phase bias offset parameters,b_(icomp) and b_(qcomp), are coupled as inputs to the in-phase andquadrature-phase bias compensation adders 406, 408, as described abovewith reference to FIG. 4. It should be understood, that although theimpairment compensator 112 illustrated in FIG. 7 has been simplified toshow only the bias compensation adders 406, 408, the impairmentcompensator 112 may include the additional elements described above withreference to FIG. 4.

Quadrature Imbalance Compensation Tracking Loop

FIG. 8 is a block diagram of a direct up-conversion transmitter chain800 having a quadrature imbalance compensation loop 802 in theimpairment compensation feedback path. This transmitter chain 800 issimilar to the transmitter chain 100 described above with reference toFIGS. 1-5, except for the inclusion of the quadrature imbalancecompensation loop 802 in the feedback path. In operation, the quadratureimbalance compensation loop 802 further compensates for phase andamplitude imbalance in the quadrature up-converter 206.

The phase and gain imbalance of the quadrature up-converter 206 isrepresented by the phase and amplitude parameters “e” and “f” asdescribed above. In order to compensate for phase and amplitudeimbalance, the I and Q components of the baseband signal are multipliedby: ${\begin{bmatrix}1 & 0 \\e & f\end{bmatrix}^{- 1} = {\begin{bmatrix}1 & 0 \\{- \frac{e}{f}} & \frac{1}{f}\end{bmatrix} = \begin{bmatrix}1 & 0 \\e_{comp} & f_{comp}\end{bmatrix}}},$where e_(comp) and f_(comp) are the desired compensation variablestracked by the quadrature imbalance compensation loop 802. If values ofthe phase and amplitude parameters, e and f, where known, then thedesired compensation variables could be calculated according to theequations: $\begin{matrix}{{e_{comp} = {- \frac{e}{f}}};{and}} \\{f_{comp} = {\frac{1}{f}.}}\end{matrix}$

Since the impairment detector 116 only calculates estimated phase andamplitude parameters, e_(e) and f_(e), however, the quadrature imbalancecompensation loop 802 applies a pre-selected quadrature balancingcoefficient K_(Q) to calculate the desired compensation variables,e_(comp) and f_(comp). The quadrature imbalance compensation loop 802may, for example, be a first order loop correction loop that generatesthe desired compensation variables, e_(comp) and f_(comp), according tothe following equations: $\begin{matrix}{{e_{comp} = {e_{comp} - {K_{Q}\frac{e_{e}}{f_{e}}}}};{and}} \\{f_{comp} = {f_{comp} + {{K_{Q}\left( {\frac{1}{f_{e}} - 1} \right)}.}}}\end{matrix}$

The desired compensation variables, e_(comp) and f_(comp), are coupledas inputs to the linear compensation block 410 of the impairmentcompensator 112, as described above with reference to FIG. 4. It shouldbe understood, that although the impairment compensator 112 illustratedin FIG. 8 has been simplified to show only the linear compensation block410, the impairment compensator 112 may include the additional elementsdescribed above with reference to FIG. 4.

Differential Timing Error Compensation Loop

FIG. 9 is a block diagram of a direct up-conversion transmitter chain900 having a differential timing error compensation loop 902 in theimpairment compensation feedback path. This transmitter chain 900 issimilar to the transmitter chain 100 described above with reference toFIGS. 1-5, except for the inclusion of the differential timing errorcompensation loop 902 in the feedback path. In operation, thedifferential timing error compensation loop 902 adjusts the I and Qcomponent delays, T_(ie) and T_(qe), to compensate for dynamic changesin the up-converter channel delays.

The differential timing error compensation loop 902 receives thein-phase and quadrature-phase component delays, T_(ie) and T_(qe),estimated by the impairment detector 116 as described above, and appliesa pre-selected timing adjustment coefficient K_(T) to generatecompensated in-phase and quadrature-phase component delays, T_(qc) andT_(ic). The differential timing error compensation loop 902 may, forexample, be implemented as a first order correction loop that generatesthe compensated component delays, T_(qc) and T_(ic), according to thefollowing equations:T_(ic)−T_(ic)+K_(T)(T_(ie)−T_(o)); andT_(qc)=T_(qc)+K_(T)(T_(ie)−T_(o)),where T_(o) is a target common delay of the in-phase andquadrature-phase channels that is pre-selected such that the delayimplemented by the impairment compensator 112 is always positive.

The compensated component delays, T_(qc) and T_(ic), are coupled asinputs to the in-phase and quadrature-phase delay compensation blocks402, 404 in the impairment compensator 112, as described above withreference to FIG. 4. It should be understood, that although theimpairment compensator 112 illustrated in FIG. 9 has been simplified toshow only the delay compensation blocks 402, 404, the impairmentcompensator 112 may include the additional elements described above withreference to FIG. 4.

Detector Temperature and Supply Voltage Compensation

FIG. 10 is a block diagram of an exemplary temperature and supplyvoltage compensation circuit 1000 for the impairment detector 116 shownin FIGS. 1, 3, and 6-9. Portions of the impairment detector 116described above may be sensitive to fluctuations in temperature andsupply voltage. These temperature and supply voltage sensitivecomponents may, for example, include the variable attenuator 302, thedown-conversion mixer 304 and the A/D converter 308 described above withreference to FIG. 3. These and any other temperature and/or voltagesensitive components are represented in FIG. 10 by the RF and IFcomponent block 1010. In addition, the temperature and supply voltagecompensation circuit 1000 also includes a band gap voltage reference1020, a temperature sensor 1030, a multiplexer 1040, a firstanalog-to-digital (A/D) converter 1050, a processor 310, and a secondanalog-to-digital (A/D) converter 1070. The temperature sensor 1030 may,for example, be a device that is sensitive to temperature and has arepeatable response and negligible hysteresis, such as a diode detector.The processor 310 may, for example, be the impairment detector processor310 described above with reference to FIG. 3.

The band gap voltage reference 1020 generates a reference voltageV_(ref). Since the band gap voltage reference 1020 is not ideal,however, the reference voltage is a function of the ambient temperatureT and the battery supply voltage V_(d).

The temperature sensor 1030 generates a temperature sensor voltage,V_(temp), which is proportional to the ambient temperature T. Since thetemperature sensor 1030 is not ideal, however, its output, V_(temp), isalso a function of the battery supply voltage V_(d).

The multiplexer 1040 is coupled to the reference voltage V_(ref), thetemperature sensor voltage V_(temp), and the battery supply voltageV_(d). In addition, the multiplexer 1040 also receives a control input1045 from the processor 310 which selects either V_(temp) or V_(d) as aselected input to the multiplexer 1040. The multiplexer 1040 thendivides the selected input, V_(temp) or V_(d), by the reference voltageV_(ref) to generate an analog ratio output R_(temp) or R_(vd), asfollows:R _(temp) =V _(temp) /V _(ref); andR _(vd) =V _(d) /V _(ref).

The selected analog ratio output, R_(temp) or R_(vd), is sampled by thefirst A/D converter 1050 and coupled as an input to the processor 310.The processor 310 may, for example, alternate between selecting V_(temp)and V_(d) as the selected input to the multiplexer 1040 in order togenerate alternating sampled R_(temp) and R_(vd) inputs to the processor310. In addition, the analog intermediate frequency (IF) signalgenerated by the temperature and supply voltage sensitive components1010 in the impairment detector is sampled by the second A/D converter1070 and coupled as an additional input to the processor 310. Inoperation, the processor 310 uses the sampled ratios, R_(temp) andR_(vd), to estimate the actual ambient temperature T and supply voltageV_(d) (the estimated values of T and V_(d) are designated herein asT_(est) and V_(dest) respectively). A method for estimating the valuesof T and V_(d) is described below with reference to FIG. 11.

The estimated temperature and supply voltage values, T_(est) andV_(dest), are used to estimate the overall gain G(T_(est), V_(dest)) ofthe analog portion of the impairment detector 116, which is a functionof both the ambient temperature T and the supply voltage V_(d). Bycomparing the estimated overall gain G(T_(est), V_(dest)) to thepre-selected desired gain of the impairment detector 116, the processor310 compensates for temperature- and supply voltage-related impairmentsin the analog IF signal by correcting one or more of the parameters inthe feedback signal 126 described above. For instance, temperature- andsupply voltage-related corrections in the analog IF signal may beimplemented by adjusting the estimated gain G_(oe), described above withreference to FIGS. 4 and 6, by a factor of G(T_(est), V_(dest)).

FIG. 11 is a flow diagram that illustrates a method 1100 for iterativelyestimating the values of the ambient temperature T and battery supplyvoltage V_(d) shown in FIG. 10. The method 1100 may, for example, beperformed by the processor 310 described above with reference to FIG.10.

The method 1100 begins in step 1110. In step 1120, the voltage value ofthe reference voltage output V_(ref) from the band gap voltage reference1020 is estimated. The reference voltage V_(ref) may be calculated, forexample, using the estimated values for the ambient temperature T_(est)and the supply voltage V_(dest), according to the following equation:V _(ref) =C ₁ +C ₂ T _(est) +C ₃ V _(dest);where C₁, C₂ and C₃ are constants that may be derived as part of acalibration process. The initial values of T_(est) and V_(dest) may bepre-selected or otherwise initialized, and therefore should be in error.In successive iterations of the method 1100, however, the values ofT_(est) and V_(dest) should converge on their respective actual values,and thus the estimated value of V_(ref) should also converge on itsactual value.

In step 1130, the estimated value of the battery supply voltage,V_(dest), is calculated. The value of V_(dest) may, for example, becalculated according to the equation:V_(dest)=R_(vd)V_(ref);where R_(vd) is a sampled ratio output from the first multiplexer 1040described above, and V_(ref) is the voltage reference output from theband gap voltage reference 1020. Similarly, in step 1140, the value ofthe temperature sensor voltage, V_(temp), as described above, isestimated according to the equation:V_(test)=R_(temp)V_(ref);where R_(temp) is a sampled ratio output from the first multiplexer1040. Then, in step 1150, the ambient temperature T is estimatedaccording to the equation:T _(est)=(V _(test) −C ₄ −C ₆ V _(dest))/C ₅;where C₄, C₅ and C₆ are constants that may be derived as part of acalibration process.

In step 1160, the estimated values, V_(dest) and T_(est), for theambient temperature T and supply voltage V_(d) are examined to determineif the values have sufficiently converged with their respective actualvalues. This step 1160 may be performed, for example, by saving thevalues of V_(dest) and T_(est) to a memory device at each iteration ofthe method 1100, and comparing the current values with stored values.The estimated values, V_(dest) and T_(est), may be deemed to havesufficiently converged when the difference between values calculated atsuccessive iterations reaches a pre-selected value. If it is determinedin step 1160 that either of the estimated values, V_(dest) or T_(est),has not sufficiently converged with its actual value, then the methodrepeats at step 1120. Otherwise, the method 1100 ends at step 1170.

Method of Operating a Feedback Compensation Detector

FIG. 12 is a flow diagram illustrating an exemplary method 1200 foroperating the feedback compensation detector described above withreference to FIGS. 1-9. The method begins in step 1210. In step 1220,the in-phase and quadrature-phase component delays T_(i) and T_(q) areestimated, as described above with reference to FIG. 5. In steps1230-1250, the matrix coefficients {a, b, c, d}, the phase, amplitudeand gain imbalances (e_(e), f_(e), and G_(oe)), and the bias offsetvalues (b_(ie) and b_(qe)) are estimated, as described above withreference to FIG. 4. Then, in step 1260, the I and Q baseband signalsare compensated using one or more of the estimated impairmentparameters, as described above with reference to FIGS. 4-9. If controlloops, such as those described above with reference to FIGS. 6-9, areutilized in the I and Q baseband signal compensation step 1260, then themethod 1280 may repeat at step 1270. Otherwise, the method 1200 ends atstep 1280.

This written description uses examples to disclose the invention,including the best mode, and also to enable any person skilled in theart to make and use the invention. The patentable scope of the inventionis defined by the claims, and may include other examples that occur tothose skilled in the art.

1. A direct up conversion transmitter chain, comprising: a basebandprocessor that generates an in-phase (I) baseband signal and aquadrature-phase (Q) baseband signal; a direct up-converter coupled tothe baseband processor that combines the I and Q baseband signals with aradio frequency (RF) carrier signal to generate an RF output signal; anantenna coupled to the direct up-converter that transmits the RF outputsignal; and an impairment detection and compensation feedback circuitcoupled to the RF output signal and the I and Q baseband signals thatdown-converts the RF output signal to generate an intermediate frequency(IF) signal, measures at least one signal impairment in the IF signal,and pre-distorts the I and Q baseband signals to compensate for themeasured signal impairment.
 2. The direct up conversion transmitterchain of claim 1, wherein the I and Q baseband signals generated by thebaseband processor are digital signals, and further comprising: a firstdigital-to-analog converter (DAC) coupled to the digital I basebandsignal that converts the digital I baseband signal into an analog Ibaseband signal; and a second DAC coupled to the digital Q basebandsignal that converts the digital Q baseband signal into an analogbaseband signal; wherein the analog I and Q baseband signals are coupledto the direct up-converter and combines with the RF carrier signal togenerate the RF output signal.
 3. The direct up conversion transmitterchain of claim 1, further comprising: a frequency synthesizer having afirst frequency output coupled to the direct up-converter and a secondfrequency output coupled to the impairment detection and compensationfeedback circuit, wherein the frequency synthesizer generates the RFcarrier signal at the first frequency output and generates a localoscillator (LO) signal at the second frequency output, wherein theimpairment detection and compensation feedback circuit uses the LOsignal to convert the RF output signal to the IF signal.
 4. The directup conversion transmitter chain of claim 1, further comprising: a bandpass filter coupled between the direct up-converter and the antenna thatfilters the RF output signal to a passband frequency range beforetransmission by the antenna.
 5. The direct up conversion transmitterchain of claim 1, wherein the impairment detection and compensationfeedback circuit includes an impairment detector coupled to the RFoutput signal that down-converts the RF output signal to generate the IFsignal, estimates the signal impairment in the IF signal, and generatesa feedback signal that is used by the impairment detection andcompensation feedback circuit to pre-distort the I and Q basebandsignals.
 6. The direct up conversion transmitter chain of claim 5,wherein the impairment detector comprises: a down-conversion mixercoupled to the RF output signal and a local oscillator (LO) signal thatcombines the RF output signal with a local oscillator (LO) signal togenerate the IF signal, wherein the frequency of the LO signal isdifferent from the frequency of the RF carrier signal; and an impairmentdetector processor coupled to the IF signal that estimates the signalimpairment in the RF output signal using the IF signal and generates thefeedback signal.
 7. The direct up-conversion transmitter chain of claim6, wherein the impairment detector further comprises: a variableattenuator coupled between the RF output signal and the down-conversionmixer that reduces the gain of the RF output signal.
 8. The directup-conversion transmitter chain of claim 6, wherein the impairmentdetector further comprises: a band pass filter coupled to thedown-conversion mixer that filters the IF signal to a passband frequencyrange to generate an analog impairment signal; and an analog-to-digitalconverter coupled to the band pass filter that samples the analogimpairment signal to generate a digital impairment signal that iscoupled to the impairment detector processor.
 9. The direct upconversion transmitter chain of claim 1, wherein the impairmentdetection and compensation feedback circuit includes an impairmentcompensator coupled between the baseband processor and the directup-converter that receives a feedback signal generated by the impairmentdetection and compensation feedback circuit and uses at least one signalimpairment parameter in the feedback signal to pre-distort the I and Qbaseband signals.
 10. The direct up conversion transmitter chain ofclaim 9, wherein the impairment detection and compensation feedbackcircuit estimates I and Q component delays in the RF output signal andgenerates I and Q delay compensation values in the feedback signal thatare proportional to the estimated I and Q component delays, and whereinthe impairment compensator comprises: an in-phase delay compensationblock that advances the I baseband signal by the I delay compensationvalue; and a quadrature-phase delay compensation block that advances theQ baseband signal by the Q delay compensation value.
 11. The direct upconversion transmitter chain of claim 9, wherein the impairmentdetection and compensation feedback circuit estimates direct-current(DC) bias in the RF output signal and generates I an Q bias offsetvalues in the feedback signal that are proportional to the estimated DCbias, and wherein the impairment compensator comprises: an in-phase biascompensation adder having a positive input coupled to the I basebandsignal and a negative input coupled to the I bias offset value thatsubtracts the bias offset value from the I baseband signal; and aquadrature-phase compensation adder having a positive input coupled tothe Q baseband signal and a negative input coupled to the Q bias offsetvalue that subtracts the bias offset value from the Q baseband signal.12. The direct up conversion transmitter chain of claim 9, wherein theimpairment detection and compensation feedback circuit estimates phaseand amplitude imbalance in the transmitter chain and generates a phaseimbalance parameter and an amplitude imbalance parameter in the feedbacksignal, and wherein the impairment compensator comprises: a linearcompensation block coupled to the I and Q baseband signals and the phaseand amplitude imbalance parameters, wherein the linear compensationblock uses the phase and amplitude imbalance parameters to apply aninverse model of the estimated phase and amplitude imbalance to the Iand Q baseband signals.
 13. The direct up conversion transmitter chainof claim 9, wherein the impairment detection and compensation feedbackcircuit estimates the overall gain of the transmitter chain andgenerates a scaling factor in the feedback signal that is a function ofthe estimated gain and a pre-selected desired gain of the transmitterchain, and wherein the impairment compensator comprises: an in-phasegain multiplier coupled to the I baseband signal and the scaling factorthat multiplies the I baseband signal by the scaling factor; and aquadrature-phase gain multiplier coupled to the Q baseband signal andthe scaling factor that multiplies the Q baseband signal by the scalingfactor.
 14. The direct up conversion transmitter chain of claim 1,wherein the impairment detection and compensation feedback circuitestimates the overall gain of the transmitter chain and generates a gainestimate, and wherein the impairment detection and compensation feedbackcircuit includes: an automatic gain control (AGC) correction loop thatcompares the gain estimate with a pre-selected desired gain of thetransmitter chain and generates a gain-compensated loop output that is afunction of the difference between the gain estimate and thepre-selected desired gain; wherein the impairment detection andcompensation feedback circuit pre-distorts the I and Q baseband signalsby multiplying the I and Q baseband signal with the gain-compensatedloop output.
 15. The direct up conversion transmitter chain of claim 1,wherein the impairment detection and compensation feedback circuitestimates direct-current (DC) bias in the RF output signal and generatesI and Q bias offset values that are proportional to the estimated DCbias, and wherein the impairment detection and compensation feedbackcircuit includes: a local oscillator (LO) leakage nulling loop thatgenerates a compensated I bias parameter as a function of the I biasoffset value and a compensated Q bias parameter as a function of the Qbias offset value; wherein the impairment detection and compensationfeedback circuit pre-distorts the I and Q baseband signals bysubtracting the compensated I bias parameter from the I baseband signaland subtracting the Q bias parameter from the Q baseband signal.
 16. Thedirect up conversion transmitter chain of claim 1, wherein theimpairment detection and compensation feedback circuit estimates phaseand amplitude imbalance in the transmitter chain and generates a phaseimbalance parameter and an amplitude imbalance parameter, and whereinthe impairment detection and compensation feedback circuit includes: aquadrature imbalance compensation loop that generates a desired phasecompensation variable as a function of the phase and amplitude imbalanceparameters and a desired amplitude compensation variable as a functionof the amplitude imbalance parameter; wherein the impairment detectionand compensation feedback circuit pre-distorts the I and Q basebandsignals by using the desired phase and amplitude compensation parametersto apply an inverse model of the estimated phase and amplitude imbalanceto the I and Q baseband signals.
 17. The direct up conversiontransmitter chain of claim 1, wherein the impairment detection andcompensation feedback circuit estimates I and Q component delays in theRF output signal and generates I and Q delay compensation values thatare proportional to the estimated I and Q component delays, and whereinthe impairment detection and compensation feedback circuit includes: adifferential timing error compensation loop that generates a compensatedI component delay as a function of the I delay compensation value and acompensated Q component delay as a function of the Q delay compensationvalue; wherein the impairment detection and compensation feedbackcircuit pre-distorts the I and Q baseband signal by advancing the Ibaseband signal by the compensated I component delay and advancing the Qbaseband signal by the compensated Q component delay.
 18. The direct upconversion transmitter chain of claim 1, wherein the direct up-convertercomprises: a quadrature up-converter having a first input coupled to theI baseband signal, a second input coupled to the Q baseband signal, anda third input coupled to the RF carrier signal, wherein the quadratureup-converter combines the I and Q baseband signals with the RF carriersignal to generate an RF quadrature up-converter output; and a poweramplifier coupled to the quadrature up-converter that increases the gainof the RF quadrature up-converter output to generate the RF outputsignal.
 19. The direct up conversion transmitter chain of claim 18,wherein the direct up-converter further comprises: an automatic gaincontrol (AGC) amplifier coupled between the quadrature up-converter thatincreases the gain of the RF quadrature up-converter output andgenerates an AGC output signal that is coupled to the power amplifier.20. The direct up conversion transmitter chain of claim 19, wherein thedirect up-converter chain further comprises: a band pass filter coupledbetween the AGC amplifier and the power amplifier that filters the AGCoutput signal prior to amplification by the power amplifier.
 21. Thedirect up conversion transmitter chain of claim 18, wherein the directup-converter further comprises: a first band pass filter coupled to theI baseband signal that filters the I baseband signal and generates afirst band pass filter output signal; a second band pass filter coupledto the Q baseband signal that filters the Q baseband signal andgenerates a second band pass filter output signal; a first amplifiercoupled to the first band pass filter that increases the gain of thefirst band pass filter output and generates a first amplifier outputsignal; and a second amplifier coupled to the second band pass filterthat increases the gain of the second band pass filter output andgenerates a second amplifier output signal; wherein the first amplifieroutput signal is coupled to the first input of the quadratureup-converter and the second amplifier output is coupled to the secondinput of the quadrature up-converter.
 22. A direct up conversiontransmitter chain, comprising: a baseband processor that generates anin-phase (I) baseband signal and a quadrature-phase (Q) baseband signal;an impairment compensator coupled to the I and Q baseband signals and afeedback signal that pre-distorts the I and Q baseband signals as afunction of at least one signal impairment parameter in the feedbacksignal and generates modified I and Q baseband signals; a directup-converter coupled to the impairment compensator that combines themodified I and Q baseband signals with a radio frequency (RF) carriersignal to generate an RF output signal; an antenna coupled to the directup-converter that transmits the RF output signal; and an impairmentdetector coupled to the RF output signal that down-converts the RFoutput signal to generate an intermediate frequency (IF) signal,estimates the signal impairment parameter from the IF signal, andgenerates the feedback signal.
 23. The direct up conversion transmitterchain of claim 22, wherein the impairment detector includes temperatureand voltage sensitive components, and further comprising: a temperaturesensor that generates a temperature sensor voltage as a function of bothan ambient temperature in the vicinity of the impairment detector and abattery supply voltage; and a processor coupled to the IF signal and thetemperature sensor voltage that estimates the signal impairmentparameter from the IF signal and adjusts the signal impairment parameterby a function of the temperature sensor voltage.